Motorola CPCI-6115 Servisní příručka stáhnout pdf (Strana 73)

Functional Description

CPCI-6200 Installation and Use (6806800J66C)

4.2 MPC8572 Integrated Processor

TheCPCI-6200 supports the MPC8572 (dual e500 core) processor. The MPC8572 is an

integrated processor with built-in DDR2/3 memory controllers (it supports two sides, up to

four banks per side), PCI Express interfaces, four 10/100/1000 Ethernet fast ports, dual

universal asynchronous receiver and transmitter (DUART), I

C controller, local bus interface,

etc.

The processor is configured to operate at 1.33 or 1.5 GHz core frequency with up to 800 MHz

data rate DDR3 memory bus.

4.3 I

C Serial Interface and Devices

The CPCI-6200 has several I

C buses, including two on the processor. The following sections

describe each bus and the serial devices connected to each bus.

4.3.1 I

C Bus 0

Bus 0 is connected between the IPMI controller and J1 connector as required by PICMG 2.0.

There is no onboard I

C device on this bus.

4.3.2 I

C Bus 1

Bus 1 is connected between the IPMI controller and J2 connector as required by PICMG 2.0.

There is no onboard I

C device on this bus.

4.3.3 I

C Bus 2

Bus 2 is connected between the IPMI controller and PCI Express expansion connector. There is

no onboard I

C device on this bus.

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 195 196

Žádné komentáře

Motorola CPCI-6115 Servisní příručka Strana 73