Motorola CPCI-6115 Servisní příručka Strana 11
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- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
List of Tables
CPCI-6200 Installation and Use (6806800J66C)
11
Table 6-40 VPCore Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 7-1 Default Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 7-2 CPCI-6200 Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 7-3 LBC Memory Map and Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 7-4 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 7-5 System Status Register, 0xF200_0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 7-6 System Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 7-7 System Control Register, 0xF200_0001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 7-8 System Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 7-9 Front Panel LED Control/Status Register, 0xF200_0002 . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 7-10 Front Panel LED Control/Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7-11 NOR Flash Control/Status Register, 0xF200_0003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7-12 NOR Flash Control/Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7-13 Interrupt Register 1, 0xF200_0004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 7-14 Interrupt Register 1 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 7-15 Interrupt Register 2, 0xF200_0005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 7-16 Interrupt Register 2 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 7-17 Interrupt Mask Register, 0xF200_0006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 7-18 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 7-19 Presence Detect Register, 0xF200_0008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 7-20 Presence Detect Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 7-21 NAND Flash Chip 1 Control Register, 0xF200_0010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 7-22 NAND Flash Chip 1 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 7-23 NAND Flash Chip 1 Select Register, 0xF200_0011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 7-24 NAND Flash Chip 1 Select Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 7-25 NAND Flash Chip 1 Presence Register, 0xF200_0012 . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 7-26 NAND Flash Chip 1 Presence Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 7-27 NAND Flash Chip 1 Status Register, 0xF200_0013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 7-28 NAND Flash Chip 1 Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 7-29 NAND Flash Chip 2 Control Register, 0xF200_0014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 7-30 NAND Flash Chip 2 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 7-31 NAND Flash Chip 2 Select Register, 0xF200_0015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 7-32 NAND Flash Chip 2 Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 7-33 NAND Flash Chip 2 Presence Register, 0xF200_0016 . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 7-34 NAND Flash Chip 2 Presence Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 7-35 NAND Flash Chip 2 Status Register, 0xF200_0017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
- CPCI-6200 1
- Trademarks 2
- Contact Address 2
- Contents 3
- List of Tables 10
- List of Figures 13
- About this Manual 15
- Conventions 18
- Summary of Changes 19
- Introduction 21
- 1.2 Standard Compliances 24
- 1.3 Mechanical Data 26
- 1.4 Ordering Information 26
- 1.5 Product Identification 27
- Chapter 2 29
- 2.1 Overview 29
- 2.4 Power Requirements 31
- 2.5 Installing Accessories 32
- PMC Filler Plate 33
- PMC Alignment 33
- Voltage Key 33
- 2.6.3 Hardware Configuration 35
- 2.10 Factory-Installed Linux 42
- Chapter 3 45
- 3.1 Board Layout 45
- 3.2 Front Panel 46
- 3.3 Connectors and Headers 47
- 3.3.1 CPCI Bus Connector, J1 48
- 3.3.2 CPCI Bus Connector, J2 49
- 3.3.4 CPCI Connector, J4 51
- 3.3.7 Ethernet Connector 58
- 3.3.8 USB Connector 58
- 3.4 Switches 66
- 3.5 Front Panel LEDs 67
- 3.6 Status Indicators 68
- Functional Description 71
- 4.4 System Memory 74
- 4.5 Timers 75
- 4.6 Ethernet Interfaces 75
- 4.7 Local Bus Interface 75
- 4.7.3 Control and Timers PLD 77
- 4.8 DUART Interface 78
- 4.9 PCI Express Port 79
- 4.10 PCI/PCI-X Bus 80
- 4.11 Operation Modes 81
- 4.11.1 System Controller Mode 82
- 4.11.2 Peripheral Mode 82
- 4.11.3 Stand Alone Mode 83
- 4.12 PCI Express Expansion 84
- 4.13 System Interrupts 85
- 4.14 Clock Distribution 86
- 4.15 MPC8572 System Clock 87
- 4.16 Reset Control Logic 87
- 4.16.1 Abort/Reset Switch 89
- 4.16.2 Reset Timing 90
- 4.17 RTC Battery 91
- 4.18 IPMI Controller 91
- 4.19 Programmable Devices 93
- 4.19.1 Local Bus Control CPLD 94
- 4.19.2 Reset CPLD 94
- 4.19.3 CPCI Control CPLD 94
- 5.4 MOTLoad Commands 96
- 5.6 MOTLoad Tests 96
- 5.7 Using MOTLoad 97
- 5.7.2 Command Line Help 99
- 5.7.3 Command Line Rules 99
- 5.8 MOTLoad Command List 100
- MOTLoad Firmware 101
- Control via IPMI 107
- 6.1.3 IPMI Messaging Commands 108
- 6.1.4 SEL Device Commands 108
- 6.1.5 SDR Repository Commands 109
- 6.1.6 FRU Inventory Commands 109
- 6.1.7 Sensor Device Commands 110
- 6.2 PICMG 2.9 Commands 111
- 6.3 Emerson Specific Commands 112
- 6.3.2 OEM Commands 115
- 6.3.2.1 BMC/PM Change Role 116
- 6.4 FRU Information 118
- 6.5 Sensor Description 118
- Memory Maps and Addresses 137
- 7.2 CPCI-6200 Memory Map 138
- 7.4 System I/O Memory Map 140
- 7.4.1 System Status Register 143
- 7.4.2 System Control Register 144
- 7.4.5 Interrupt Register 1 148
- 7.4.6 Interrupt Register 2 149
- 7.4.7 Interrupt Mask Register 150
- 7.4.23 PLD Revision Register 167
- 7.4.24 PLD Date Code Register 168
- 7.4.25 Test Register 1 168
- 7.4.26 Test Register 2 169
- 7.4.27.2 Control Registers 170
- 7.4.27.3 Compare Registers 171
- 7.4.27.4 Counter Registers 172
- 7.5 Interrupt Controller 173
- C Device Addresses 174
- 7.7 PCI/PCI-X Configuration 175
- Replacing the Battery 179
- A.2 Replacing the Battery 180
- Related Documentation 181
- B.3 Related Specifications 183
- Safety Notes 185
- Installation 186
- Operation 187
- Hot Swap 188
- Sicherheitshinweise 189
- System Installation 191
- Batterie 192
- © 2009 Emerson Electric Co 196
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