Block Diagram
http://www.motorola.com/computer/literature 3-17
3
VMEP∗ VMEbus present. If set, there is no VMEbus interface. If
cleared, the VMEbus interface is supported.
LANP
∗ Ethernet present. If set, no Ethernet transceiver interface is
installed. If cleared, there is on-board Ethernet support.
SCSIP
∗ SCSI present. If set, there is no on-board SCSI interface. If
cleared, on-board SCSI is supported.
P2 Signal Multiplexing
Due to the limited supply of available pins in the P2 backplane connectors
of MVME2700 models that are configured for MVME761 I/O mode,
certain signals are multiplexed through VMEbus connector P2 for
additional I/O capacity.
The signals affected are synchronous I/O control signals that pass between
the base board and the MVME761 transition module. The multiplexing is
a hardware function that is entirely transparent to software.
Four signals are involved in the P2 multiplexing function: MXDO, MXDI,
MXCLK, and MXSYNC
∗.
MXDO is a time-multiplexed data output line from the main board and
MXDI is a time-multiplexed line from the MVME761 module. MXCLK
is a 10 MHz bit clock for the MXDO and MXDI data lines. MXSYNC
∗ is
asserted for one bit time at time slot 15 (refer to the following table) by the
MVME2700 base board. The MVME761 transition module uses
MXSYNC
∗ to synchronize with the base board.
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