
Exception Processing, System Control Operations, and I/O 169
31 24
Register Contents
23 1G 15 0
7 0
hi-order
low-order
Contents of Memory
15
B 7
0
hi-order
low-order
find that an instruction is to be substituted by one that requires one less
word in memory, a NOP can be used to fill the excess word.
The RESET instruction can only be used in supervisor mode. When
it is executed it asserts the hardware reset line. This normally causes all
external devices to be reset. The exact results of using this instruction
will depend on what sort of devices are connected to the hardware reset
line. Normally this instruction is executed by the operating system to
ensure an initialized state for all external devices. Unless you are writing
an operating system, you should never have need for this instruction. If
you execute it by mistake in the user mode, a trap will be generated.
The STOP instruction has the general form:
STOP #xxx
The STOP instruction must be executed when in the supervisor mode
or else a trap will be generated. The immediate operand of the STOP
instruction is moved into the entire status register, the program counter is
advanced to the next instruction, and the CPU stops executing. However,
if an interrupt occurs with a priority higher than the current interrupt
priority level in the SR, then an interrupt exception will be generated;
otherwise nothing happens. If the exception handler executes an RTE,
the next instruction following the STOP will be executed. If an external
reset is generated, the processor will execute the standard reset sequence.
The test and set instruction, TAS, is primarily used in a multi-processor
environment. The general form of the instruction is:
TAS <ea>
The operand size used with the TAS instruction must be byte. It first tests
the byte at the effective address and sets the N and Z bits of the CCR
accordingly. It then sets bit 7 of the operand to a 1. This instruction is
special in that a read-modify-write bus cycle is used so that the test and
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