Motorola MPC5200 Uživatelský manuál

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© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Freescale Semiconductor
Data Sheet
MPC5200
Rev. 4, 01/2005
“Definitive Data: Freescale reserves the right to change the production detail specifications
as may be required to permit improvements in the design of its products.”
Table of Contents
NOTE
The information in this
document is subject to
change. For the latest data
on the MPC5200, visit
www.freescale.com and
proceed to the MPC5200
Product Summary Page.
1 Overview
The MPC5200 integrates a high performance MPC603e
series G2_LE core with a rich set of peripheral functions
focused on communications and systems integration.
The G2_LE core design is based on the PowerPC
TM
core
architecture. MPC5200 incorporates an innovative
BestComm I/O subsystem, which isolates routine
maintenance of peripheral functions from the embedded
G2_LE core. The MPC5200 contains a SDRAM/DDR
Memory Controller, a flexible External Bus Interface,
PCI Controller, USB, ATA, Ethernet, six Programmable
Serial Controllers (PSC), I
2
C, SPI, CAN, J1850, Timers,
and GPIOs.
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Electrical and Thermal Characteristics . . . . . . . . . 6
3.1 DC Electrical Characteristics . . . . . . . . . . . . . 6
3.2 Oscillator and PLL Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 AC Electrical Characteristics . . . . . . . . . . . . 14
4 Package Description . . . . . . . . . . . . . . . . . . . . . . 64
4.1 Package Parameters . . . . . . . . . . . . . . . . . . 64
4.2 Mechanical Dimensions. . . . . . . . . . . . . . . . 64
4.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . 66
5 System Design Information. . . . . . . . . . . . . . . . . 71
5.1 Power UP/Down Sequencing . . . . . . . . . . . 71
5.2 System and CPU Core AVDD power
supply filtering . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Pull-up/Pull-down Resistor Requirements . . 73
5.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 79
7 Document Revision History. . . . . . . . . . . . . . . . . 79
MPC5200 Data Sheet
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Strany 1 - MPC5200 Data Sheet

© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.Freescale SemiconductorData SheetMPC5200Rev. 4, 01/2005“Definitive Data: Freescale re

Strany 2 - 2Features

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor10where N is the number of output pins switching in a group M,

Strany 3 - Freescale Semiconductor 3

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 113.1.6 Thermal Characteristics3.1.7 Heat DissipationAn estima

Strany 4 - • Test/Debug features

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor12Historically, the thermal resistance has frequently been expr

Strany 5 - Freescale Semiconductor 5

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 13There is a separate oscillator for the independent Real-Time

Strany 6

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor143.2.4 G2_LE Core PLL Electrical CharacteristicsThe internal c

Strany 7 - (see Table 2)

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 15• TA = -40 to 85 oC• Tj = -40 to 115 oC• VDD_CORE = 1.42 to

Strany 8

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor163.3.3 ResetsThe MPC5200 has three reset pins: •PORRESET - Pow

Strany 9 - 3.1.5 Power Dissipation

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 17For additional information, see the MPC5200 User Manual [1].

Strany 10

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor18NOTEBeware of changing the values on the pins of the reset co

Strany 11 - 3.1.7 Heat Dissipation

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 19Notes:1) The frequency of IP_CLK depends on register setting

Strany 12 - Freescale Semiconductor12

MPC5200 Data Sheet, Rev. 4FeaturesFreescale Semiconductor22FeaturesKey features are shown below.• MPC603e series G2_LE core— Superscalar architecture—

Strany 13

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor203.3.5 SDRAM3.3.5.1 Memory Interface Timing-Standard SDRAM Rea

Strany 14

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 21Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing3

Strany 15 - 3.3.2 Clock AC Specifications

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor22Table 20. DDR SDRAM Memory Read TimingSym Description Min Max

Strany 16 - 3.3.3 Resets

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 23Figure 7. Timing Diagram—DDR SDRAM Memory Read TimingMEM_CLK

Strany 17

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor24Figure 8. Read Data sample window depend on the number of Tap

Strany 18 - 3.3.4 External Interrupts

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 253.3.5.4 Memory Interface Timing-DDR SDRAM Write CommandFigur

Strany 19 - GPIO_PSC3_4

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor26Figure 10. PCI CLK WaveformNOTES:1. In general, all 66-MHz PC

Strany 20 - 3.3.5 SDRAM

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 27NOTES:1. See the timing measurement conditions in the PCI Lo

Strany 21 - Row Column

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor283.3.7 Local Plus BusThe Local Plus Bus is the external bus in

Strany 22

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 29NOTES:1. ACK can shorten the CS pulse width.Wait States (WS)

Strany 23

FeaturesMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 3— CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97— Full duplex SPI mo

Strany 24

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor303.3.7.2 Burst ModeTable 25. Burst Mode TimingNOTES:1. Wait St

Strany 25 - 3.3.6 PCI

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 31Figure 13. Timing Diagram—Burst ModeADDRDATA (rd)CS[x]R/WOET

Strany 26

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor323.3.7.3 MUXed ModeNote: 1. ACK can shorten the CS pulse wid

Strany 27

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 33Figure 14. Timing Diagram—MUXed Mode3.3.8 ATAThe MPC5200 ATA

Strany 28 - 3.3.7 Local Plus Bus

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor34The MPC5200 ATA Host Controller design makes data available c

Strany 29

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 35Figure 15. PIO Mode TimingTable 28. Multiword DMA Timing Spe

Strany 30 - 3.3.7.2 Burst Mode

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor36Figure 16. Multiword DMA TimingTable 29. Ultra DMA Timing Spe

Strany 31

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 37(t)LI015001500150Limited Interlock time.1,2A8.34(t)MLI20 — 2

Strany 32 - 3.3.7.3 MUXed Mode

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor38Figure 17. Timing Diagram—Initiating an Ultra DMA Data In Bur

Strany 33 - 3.3.8 ATA

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 39Figure 19. Timing Diagram—Host Pausing an Ultra DMA Data In

Strany 34

MPC5200 Data Sheet, Rev. 4FeaturesFreescale Semiconductor4• Test/Debug features— JTAG (IEEE 1149.1 test access port)— Common On-chip Processor (COP) d

Strany 35 - Figure 15. PIO Mode Timing

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor40Figure 21. Timing Diagram—Host Terminating Ultra DMA Data In

Strany 36

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 41Figure 22. Timing Diagram—Initiating an Ultra DMA Data Out B

Strany 37

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor42Figure 24. Timing Diagram—Drive Pausing an Ultra DMA Data Out

Strany 38

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 43Figure 26. Timing Diagram—Drive Terminating Ultra DMA Data O

Strany 39

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor443.3.9 EthernetAC Test Timing Conditions:• Output LoadingAll O

Strany 40

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 45Figure 29. Ethernet Timing Diagram—MII Tx SignalFigure 30. E

Strany 41

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor46Figure 31. Ethernet Timing Diagram—MII Serial Management3.3.1

Strany 42

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 47NOTEOutput timing was specified at a nominal 50 pF load.Figu

Strany 43

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor48Figure 33. Timing Diagram — SPI Master Mode, Format 0 (CPHA =

Strany 44 - 3.3.9 Ethernet

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 49Figure 34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA =

Strany 45

FeaturesMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 5Figure 1. Simplified Block Diagram—MPC5200 603G2_LE CoreSDRAM / DDRJTAG / COPInterfaceReset

Strany 46 - 3.3.10 USB

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor50Figure 35. Timing Diagram — SPI Master Mode, Format 1 (CPHA =

Strany 47 - 3.3.11 SPI

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 51Figure 36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA =

Strany 48

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor52NOTEOutput timing was specified at a nominal 50 pF load.Figur

Strany 49

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 533.3.15 PSC3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mod

Strany 50

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor54Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S

Strany 51 - 3.3.13 I

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 55Figure 39. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S

Strany 52 - 3.3.14 J1850

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor56Figure 40. Timing Diagram — AC97 Mode3.3.15.3 IrDA ModeNOTEOu

Strany 53 - 3.3.15 PSC

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 573.3.15.4 SPI ModeNOTEOutput timing was specified at a nomina

Strany 54

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor58NOTEOutput timing was specified at a nominal 50 pF load.Figur

Strany 55 - 3.3.15.2 AC97 Mode

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 59NOTEOutput timing was specified at a nominal 50 pF load.Figu

Strany 56 - 3.3.15.3 IrDA Mode

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor63 Electrical and Thermal Characteristics3.1 DC Electrical Char

Strany 57 - 3.3.15.4 SPI Mode

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor60NOTEOutput timing was specified at a nominal 50 pF load.Figur

Strany 58

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 613.3.16 GPIOs and Timers3.3.16.1 General and Asynchronous Sig

Strany 59

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor623.3.17 IEEE 1149.1 (JTAG) AC SpecificationsFigure 47. Timing

Strany 60

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 63Figure 48. Timing Diagram—JTAG TRSTFigure 49. Timing Diagram

Strany 61 - 3.3.16 GPIOs and Timers

MPC5200 Data Sheet, Rev. 4Package DescriptionFreescale Semiconductor644 Package Description 4.1 Package ParametersThe MPC5200 uses a 27 mm x 27 mm TE-

Strany 62

Package DescriptionMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 65Figure 51. Mechanical Dimensions and Pinout Assignments for the MPC5200, 272 TE

Strany 63 - OUTPUT DATA VALID

MPC5200 Data Sheet, Rev. 4Package DescriptionFreescale Semiconductor664.3 Pinout ListingsSee details in the MPC5200 User Manual [1]. Table 52. MPC5200

Strany 64 - 4 Package Description

Package DescriptionMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 67PCI_TRDYI/O VDD_IO PCI PCILocal PlusLP_ACK I/O VDD_IO DRV8 TTL PULLUPLP_ALEI/O

Strany 65 - DATE 10/15/1997

MPC5200 Data Sheet, Rev. 4Package DescriptionFreescale Semiconductor68ETH_8 RX_DV I/O VDD_IO DRV4 TTLETH_9 CD, RX_CLK I/O VDD_IO DRV4 SchmittETH_10 CT

Strany 66 - 4.3 Pinout Listings

Package DescriptionMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 69I2C_3 SDA I/O VDD_IO DRV4 SchmittPSCPSC1_0 TxD, Sdata_out, MOSI, TXI/O VDD_IO D

Strany 67

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 73.1.3 DC Electrical SpecificationsTable 3 gives the DC Electr

Strany 68

MPC5200 Data Sheet, Rev. 4Package DescriptionFreescale Semiconductor70TIMER_1 I/O VDD_IO DRV4 TTLTIMER_2 MOSI I/O VDD_IO DRV4 TTLTIMER_3 MISO I/O VDD_

Strany 69

System Design InformationMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 715 System Design Information5.1 Power UP/Down SequencingFigure 52 shows si

Strany 70

MPC5200 Data Sheet, Rev. 4System Design InformationFreescale Semiconductor72Figure 52. Supply Voltage SequencingThe relationship between VDD_IO_MEM an

Strany 71 - 5 System Design Information

System Design InformationMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 73VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then

Strany 72 - 5.1.1 Power Up Sequence

MPC5200 Data Sheet, Rev. 4System Design InformationFreescale Semiconductor745.3.2 Pull-up Requirements for the PCI Control LinesIf the PCI interface i

Strany 73 - 5.1.2 Power Down Sequence

System Design InformationMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 75Figure 54. PORRESET vs. JTAG_TRST 5.4.1.2 Connecting JTAG_TRSTThe wiring

Strany 74 - 5.4 JTAG

MPC5200 Data Sheet, Rev. 4System Design InformationFreescale Semiconductor76For a board with a COP (common on-chip processor) connector, which accesse

Strany 75 - 5.4.2 G2_LE COP/BDM Interface

System Design InformationMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 77Figure 55. COP Connector Diagram1357911131524681012K16KeyKey 14HRESETSRES

Strany 76

MPC5200 Data Sheet, Rev. 4System Design InformationFreescale Semiconductor785.4.2.2 Boards without COP connectorIf the JTAG interface is not used, JTA

Strany 77 - Physical Pinout

Ordering InformationMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 796 Ordering Information7 Document Revision HistoryTable 55 provides a revision

Strany 78 - Freescale Semiconductor78

MPC5200 Data Sheet, Rev. 4Electrical and Thermal CharacteristicsFreescale Semiconductor8Input leakage current Vin = 0 or VDD_IO/VDD_IO_MEMSDR(dependin

Strany 79 - 7 Document Revision History

MPC5200Rev. 4, 01/2005How to Reach Us:Home Page:www.freescale.comE-mail:[email protected]/Europe or Locations Not Listed:Freescale Semiconducto

Strany 80 - How to Reach Us:

Electrical and Thermal CharacteristicsMPC5200 Data Sheet, Rev. 4Freescale Semiconductor 93.1.4 Electrostatic DischargeCAUTIONThis device contains circ

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