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Motorola MPC8260 manuály

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Motorola MPC8260 Uživatelský manuál (1006 strany)


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Tabulka s obsahem

MPC8260 PowerQUICC II

1

UserÕs Manual

1

CONTENTS

10

ILLUSTRATIONS

33

MOTOROLA Tables xlv

45

MOTOROLA Tables xlvii

47

MOTOROLA Tables xlix

49

MOTOROLA Tables li

51

MOTOROLA Tables liii

53

About This Book

55

Organization

56

MOTOROLA About This Book lvii

57

MOTOROLA About This Book lxv

65

Chapter 1

71

1.2.1 MPC603e Core

75

1.3.1 Signals

77

1.5 Serial Protocol Table

79

1.6 MPC8260 ConÞgurations

80

1.7.1.1 Remote Access Server

81

1.7.2 Bus ConÞgurations

85

1.7.2.1 Basic System

85

Chapter 2

89

PowerPC Processor Core

89

Instruction Unit

90

2.2.1 Instruction Unit

93

2.2.4.1 Integer Unit (IU)

94

2.2.5 Completion Unit

95

2.3 Programming Model

96

2.3.1.1 PowerPC Register Set

97

Part I. Overview

100

2.4 Cache Implementation

106

2.4.2.1 Data Cache

107

2.4.2.2 Instruction Cache

109

2.4.2.3 Cache Locking

109

2.5 Exception Model

110

2.6 Memory Management

114

2.6.1 PowerPC MMU Model

115

2.7 Instruction Timing

117

PowerPC 603e Microprocessor

118

Chapter 3

121

Memory Map

121

ConÞguration and Reset

135

Conventions

136

Acronyms and Abbreviations

136

Chapter 4

139

System Interface Unit (SIU)

139

4.1.1 Bus Monitor

141

4.1.2 Timers Clock

142

4.1.3 Time Counter (TMCNT)

142

Figure 4-5. PIT Block Diagram

143

4.2 Interrupt Controller

145

4.2.1 Interrupt ConÞguration

146

1 Highest Ñ

147

2 XSIU1 No (TMCNT,PIT = Yes)

147

4.3 Programming Model

155

Figure 4-14. SIPNR_H Fields

159

Figure 4-15. SIPNR_L Fields

159

Figure 4-16. SIMR_H Register

160

Figure 4-17. SIMR_L Register

161

Figure 4-22. PPC_ACR

166

LCL_ACRL)

168

Figure 4-27. LCL_ALRL

169

(TESCR1)

174

(TESCR2)

175

(L_TESCR1)

176

(L_TESCR2)

177

4.4 SIU Pin Multiplexing

182

Table 4-24

183

Chapter 5

185

5.1.1 Reset Actions

186

5.1.2 Power-On Reset Flow

186

5.1.3 HRESET Flow

187

5.1.4 SRESET Flow

187

MPC8260Õs SIU register map

188

5.4 Reset ConÞguration

190

Part III

197

The Hardware Interface

197

Suggested Reading

198

UPM User-programmable machine

201

Term Meaning

201

Chapter 6

203

External Signals

203

Table 6-1. External Signals

205

Chapter 7

215

60x Signals

215

7.1 Signal ConÞguration

216

7.2 Signal Descriptions

217

7.2.1.2 Bus Grant (BG)

218

7.2.2.1 Transfer Start (TS)

220

7.2.4.4 Global (GBL)

223

7.2.6.1 Data Bus Grant (DBG)

226

7.2.6.2 Data Bus Busy (DBB)

227

7.2.7 Data Transfer Signals

227

7.2.7.1 Data Bus (D[0Ð63])

227

Chapter 8

233

The 60x Bus

233

8.2 Bus ConÞguration

234

8.3.1 Arbitration Phase

237

8.4.1 Address Arbitration

239

8.4.2 Address Pipelining

241

Table 8-5. Burst Ordering

246

Figure 8-7. Retry Cycle

256

8.5 Data Tenure Operations

258

8.5.2 Data Streaming Mode

259

8.7 Processor State Signals

264

8.8 Little-Endian Mode

265

Chapter 9

267

Clocks and Power Control

267

9.2 Clock ConÞguration

268

9.3 External Clock Inputs

271

9.4 Main PLL

271

9.5 Clock Dividers

272

9.7 PLL Pins

273

Section 9.4, ÒMain PLL.Ó

275

9.10 Basic Power Structure

276

Chapter 10

277

Memory Controller

277

10.1 Features

279

10.2 Basic Architecture

281

MxMR[BS]

282

10.2.2 Page Hit Checking

285

10.2.8 Atomic Bus Operation

286

10.2.9 Data Pipelining

286

Internal

289

10.3.1 Base Registers (BRx)

290

Figure 10-8. ORx ÑGPCM Mode

294

Figure 10-9. ORxÑUPM Mode

296

REFRESH

298

ACTIVATE or REFRESH command

298

READ/WRITE command after an

298

ACTIVATE

299

RUN command)

304

WRITE or READ command is

305

10.4 SDRAM Machine

309

PRECHARGE-ALL-BANKS command

311

CBR REFRESH commands

311

10.4.5 Bank Interleaving

312

PRECHARGE

315

Figure 10-26. EAMUX = 1

318

Figure 10-27. BUFCMD = 1

318

ODE-SET Command Timing

322

10.4.10 SDRAM Refresh

323

10.4.11 SDRAM Refresh Timing

323

ACTIVATE command, its address

325

10.5.1 Timing ConÞguration

328

ACS = 11

329

ACS = 10

329

CSNT = 1

330

10.5.1.3 Relaxed Timing

331

RUN command

339

10.6.1 Requests

340

RUN Command

342

10.6.3 Clock Timing

343

Clock Ratios

344

10.6.4 The RAM Array

345

10.6.4.1 RAM Words

346

RUN command RLFx

352

10.6.4.4 Signals Negation

354

10.6.4.5 The Wait Mechanism

354

ACTIVATE command

356

Figure 10-74. Exception Cycle

365

Wait States

371

10.8.2 Slow Devices Example

376

Chapter 11

383

Secondary (L2) Cache Support

383

11.1.2 Write-Through Mode

384

11.1.3 ECC/Parity Mode

386

Interface

389

11.4 L2 Cache Operation

389

11.5 Timing Example

390

Chapter 12

393

IEEE 1149.1 Test Access Port

393

12.2 TAP Controller

394

12.3 Boundary Scan Register

395

12.4 Instruction Register

420

12.5 MPC8260 Restrictions

422

12.6 Nonscan Chain Operation

422

Intended Audience

423

Contents

423

Part IV-ii MOTOROLA

424

Part IV-vi MOTOROLA

428

Part IV-viii MOTOROLA

430

Chapter 13

431

Overview

431

13.3.1 Features

434

13.3.2 CP Block Diagram

434

13.3.4 Peripheral Interface

436

13.3.5 Execution from RAM

437

13.4 Command Set

441

13.4.1.1 CP Commands

443

13.5 Dual-Port RAM

445

13.5.2 Parameter RAM

447

13.6 RISC Timer Tables

448

SET TIMER to

449

SET TIMER

451

SET TIMER Command

452

SET TIMER command

453

Chapter 14

455

Figure 14-1. SI Block Diagram

456

14.1 Features

457

14.2 Overview

458

14.4 Serial Interface RAM

462

14.6.1 IDL Interface Example

480

Figure 14-23. IDL Bus Signals

482

Table 14-11. GCI Signals

485

Figure 14-24. GCI Bus Signals

486

14.7.2.2 SCIT Programming

487

Chapter 15

491

CPM Multiplexing

491

15.1 Features

492

15.3 NMSI ConÞguration

494

Figure 15-3. Bank of Clocks

495

15.4 CMX Registers

496

Chapter 16

509

Baud-Rate Generators (BRGs)

509

Chapter 17

515

17.1 Features

516

17.2.1 Cascaded Mode

517

Chapter 18

525

18.2 SDMA Registers

527

18.3 IDMA Emulation

529

18.4 IDMA Features

529

18.5 IDMA Transfers

530

Transfer (Size = 128 Bytes)

532

18.5.1.2 Normal Mode

533

STOP_IDMA

534

18.6 IDMA Priorities

536

18.7 IDMA Interface Signals

536

18.7.1 DREQx and DACKx

537

18.7.1.2 Edge-Sensitive Mode

537

18.8 IDMA Operation

538

START_IDMA command is issued

539

18.8.2 IDMAx Parameter RAM

540

START_IDMA command

541

DCM is undeÞned at reset

542

18.8.3 IDMA Performance

546

18.8.5 IDMA BDs

547

START_IDMA Command

550

STOP_IDMA Command

550

18.10 IDMA Bus Exceptions

551

START_IDMA

554

Chapter 19

557

19.1 Features

558

Figure 19-3 shows GSMR_L

562

ENTER HUNT MODE

564

CLOSE RXBD

564

19.3 SCC Parameter RAM

569

19.3.1 SCC Base Addresses

571

19.3.4 Initializing the SCCs

573

Table 19-9. DPLL Codings

581

19.3.8 ReconÞguring the SCCs

582

19.3.8.5 Switching Protocols

583

19.3.9 Saving Power

583

Chapter 20

585

SCC UART Mode

585

20.1 Features

586

20.3 Synchronous Mode

587

20.4 SCC UART Parameter RAM

588

20.7 SCC UART Commands

590

Table 20-3. Receive Commands

591

20.10 Hunt Mode (Receiver)

594

Data Stream

594

STOP TRANSMIT

595

TRANSMIT

595

Table 20-8. Reception Errors

597

Register (SCCM)

603

SCCM for UART operation

604

GRACEFUL

605

Bits Name Description

606

0 The line is not idle

606

1 The line is idle

606

Chapter 21

609

SCC HDLC Mode

609

21.1 SCC HDLC Features

610

21.4 SCC HDLC Parameter RAM

611

21.6 SCC HDLC Commands

613

Table 21-3. Receive Commands

614

Table 21-4. Transmit Errors

614

Table 21-5. Receive Errors

614

21.14.1 HDLC Bus Features

627

21.14.4 Delayed RTS Mode

629

Chapter 22

633

SCC BISYNC Mode

633

22.1 Features

634

22.5 SCC BISYNC Commands

637

Sequence

641

Table 22-8. Transmit Errors

642

Table 22-9. Receive Errors

642

Figure 22-6. SCC BISYNC RxBD

644

ENTER HUNT MODE command

648

Chapter 23

653

SCC Transparent Mode

653

ENTER HUNT MODE

655

Table 23-4. Receive Commands

660

Table 23-5. Transmit Errors

660

Table 23-6. Receive Errors

660

Descriptions

661

Descriptions (Continued)

662

Chapter 24

669

SCC Ethernet Mode

669

24.1 Ethernet on the MPC8260

670

24.2 Features

671

RESTART TRANSMIT command, it

674

Table 24-1

676

SET GROUP

677

24.9 SCC Ethernet Commands

678

Table 24-3. Receive Commands

679

24.11 Hash Table Algorithm

681

24.12 Interpacket Gap Time

681

24.13 Handling Collisions

681

RESTART TRANSMIT command

682

RESTART

682

Table 24-5. Reception Errors

683

Field Descriptions

685

INIT RX AND TX PARAMETERS

691

Chapter 25

693

SCC AppleTalk Mode

693

25.2 Features

694

25.3 Connecting to AppleTalk

695

25.4.2 Programming the PSMR

696

25.4.3 Programming the TODR

696

Chapter 26

697

26.1 Features

698

26.2.3 SMC Parameter RAM

702

CLOSE RXBD command

703

26.3 SMC in UART Mode

706

26.3.1 Features

707

Table 26-4. Transmit Commands

708

26.3.6 Sending a Break

709

26.3.7 Sending a Preamble

709

26.3.9 SMC UART RxBD

710

26.3.10 SMC UART TxBD

712

Figure 26-8. SMC UART TxBD

713

26.4 SMC in Transparent Mode

716

26.4.1 Features

717

26.4.8 SMC Transparent RxBD

722

26.4.9 SMC Transparent TxBD

723

26.5 The SMC in GCI Mode

726

TIMEOUT command

727

26.5.4 SMC GCI Commands

728

Chapter 27

731

27.3 Global MCC Parameters

733

27.5 Super-Channel Table

735

Figure 27-6. TSTATE High Byte

739

Figure 27-7. INTMSK Mask Bits

740

27.9 MCC Commands

746

27.10 MCC Exceptions

747

Reset 0000_0000_0000_0000

748

27.11 MCC Buffer Descriptors

751

Invalid data

752

Chapter 28

759

28.1 Overview

760

GFMR format

761

(FPSMRx)

765

28.6 FCC Buffer Descriptors

766

28.7 FCC Parameter RAM

768

28.9 FCC Initialization

772

28.10 FCC Interrupt Handling

773

28.11 FCC Timing Control

773

Figure 28-8. CTS Lost

776

28.13 Saving Power

779

Chapter 29

781

ATM Controller

781

29.1 Features

782

29.2 ATM Controller Overview

784

29.2.1 Transmitter Overview

785

29.2.2 Receiver Overview

786

29.2.4 ABR Flow Control

788

Table 29-1. ATM Service Types

789

Cells per Slot

790

Number of Slots

790

Current Slot

790

Cell Rescheduling

790

PCR = 1 PCR_FRACTION = 62

792

Conforming VBR Traffic

792

29.4.1 External CAM Lookup

794

29.4.2 Address Compression

795

29.4.3 Misinserted Cells

798

29.5.1 The ABR Model

800

29.5.1.3 ABR Flowcharts

802

29.5.2 RM Cell Structure

805

29.6 OAM Support

807

29.6.6.2 PM Block Monitoring

810

29.6.6.3 PM Block Generation

811

29.7 User-DeÞned Cells (UDC)

812

29.8 ATM Layer Statistics

813

29.9.3 Timing Issues

816

29.9.6 CAS Support

816

29.10 ATM Memory Structure

817

29.10.2.1 ATM Channel Code

822

command is needed

832

command. When the host

832

Specific

836

29.10.4 APC Data Structure

841

29.10.4.2 APC Priority Table

843

29.10.5.4 AAL5 RxBD

849

29.10.5.5 AAL1 RxBD

851

29.10.5.6 AAL0 RxBD

852

29.10.5.8 AAL5 TxBDs

854

29.10.5.9 AAL1 TxBDs

856

29.10.5.10 AAL0 TxBDs

857

29.10.7 UNI Statistics Table

858

29.11 ATM Exceptions

859

Figure 29-56 shows an entry

860

29.12 The UTOPIA Interface

862

29.13 ATM Registers

865

29.14 ATM Transmit Command

870

External Logic

871

CPM Performance

872

29.16.2 APC ConÞguration

873

29.16.3 Buffer ConÞguration

873

Chapter 30

875

Fast Ethernet Controller

875

30.2 Features

877

GRACEFUL STOP

880

30.6 Flow Control

882

30.7 CAM Interface

882

30.8 Ethernet Parameter RAM

883

30.9 Programming Model

886

30.10 Ethernet Command Set

886

Table 30-4. Receive Commands

887

30.11 RMON Support

888

30.13 Hash Table Algorithm

891

30.14 Interpacket Gap Time

892

30.15 Handling Collisions

892

Table 30-7. Reception Errors

893

30.19 Ethernet RxBDs

897

30.20 Ethernet TxBDs

900

Chapter 31

903

FCC HDLC Controller

903

31.1 Key Features

904

GRACEFUL STOP TRANSMIT

905

31.4 HDLC Parameter RAM

906

31.5 Programming Model

907

31.5.2 HDLC Error Handling

908

GRACEFUL STOP TRANSMIT

917

Chapter 32

921

FCC Transparent Controller

921

32.1 Features

922

Field 8-Bit Sync Pattern Ñ

923

Field 16-Bit Sync Pattern

923

Chapter 33

925

33.1 Features

926

— 0_0000_0000

930

NOTE: Q = Undefined Signal

931

33.5 SPI Parameter RAM

934

33.6 SPI Commands

936

INIT RX

937

PARAMETERS

937

Figure 33-11. SPI RxBD

938

Figure 33-12. SPI TxBD

939

Chapter 34

943

C Controller

943

34.1 Features

944

C Controller Transfers

945

Figure 34-4. I

946

C Master Write Timing

946

34.3.4 I

947

C Multi-Master Considerations

947

C Registers

948

34.4.2 I

949

C Address Register (I2ADD)

949

34.4.3 I

949

34.4.4 I

950

34.4.5 I

950

C Command Register (I2COM)

950

C Parameter RAM

951

Table 34-6. I

952

C Commands

953

34.7 The I

954

34.7.1.1 I

955

34.7.1.2 I

956

Chapter 35

957

Parallel I/O Ports

957

35.2 Port Registers

958

35.3 Port Block Diagram

962

35.4 Port Pins Functions

962

35.5 Ports Tables

963

35.6 Interrupts from Port C

975

Appendix A

977

Appendixes

978

A.3 MPC8260-SpeciÞc SPRs

979

Numerics

981

ATM TRANSMIT command, 29-90

982

Attention!

1005




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